{"id":16324,"date":"2026-01-13T17:36:21","date_gmt":"2026-01-13T12:06:21","guid":{"rendered":"https:\/\/theeducationoverview.in\/?p=16324"},"modified":"2026-01-13T17:36:21","modified_gmt":"2026-01-13T12:06:21","slug":"design-linked-incentive-scheme","status":"publish","type":"post","link":"https:\/\/theeducationoverview.in\/?p=16324","title":{"rendered":"Design Linked Incentive Scheme"},"content":{"rendered":"

Design Linked Incentive Scheme<\/strong><\/span><\/h2>\n

\nCatalyzing India\u2019s Semiconductor Design Ecosystem<\/strong><\/span><\/h3>\n

Posted On: 04 JAN 2026 12:18PM by PIB Delhi<\/strong><\/span><\/p>\n

Key Takeaways<\/strong><\/span><\/p>\n

    \n
  • Semiconductor chip\u00a0design is the main value driver, contributing up to\u00a050% of value addition,\u00a020\u201350% of Bill of Materials\u00a0cost (BOM), and\u00a030\u201335% of global semiconductor sales\u00a0via the fabless segment.<\/strong><\/span><\/li>\n
  • MeitY\u2019s Design Linked Incentive (DLI) Scheme\u00a0under the\u00a0Semicon India Programme\u00a0aims to build a\u00a0self-reliant, globally competitive chip design ecosystem.<\/strong><\/span><\/li>\n
  • 24 DLI-supported chip design projects\u00a0target\u00a0strategic sectors\u00a0including video surveillance, drone detection, energy metering, microprocessors, satellite communications, and IoT SoCs.<\/strong><\/span><\/li>\n
  • DLI supported projects are scaling rapidly, with\u00a016 tape-outs,\u00a06 ASICs chips,\u00a010 patents,\u00a01,000+ engineers engaged, and\u00a0over 3\u00d7 private investment leveraged.<\/strong><\/span><\/li>\n<\/ul>\n

    Introduction<\/strong><\/span><\/p>\n

    India is rapidly advancing its semiconductor ambitions, recognizing semiconductor chips as critical enablers of healthcare, transport, communications, defence, space, and emerging digital infrastructure. With accelerating digitalization and automation, global demand for semiconductor chips is rising sharply. In response, the Government of India, through the\u00a0Semicon India Programme\u00a0and the\u00a0India Semiconductor Mission (ISM),\u00a0is strengthening the domestic semiconductor ecosystem and supply chain. However, semiconductor manufacturing remains concentrated in a limited number of geographies, making global supply chains highly fragile and vulnerable to disruptions. This underscores the urgent need to diversify the global manufacturing base, with India increasingly emerging as a strategic and reliable player in the global semiconductor landscape.<\/strong><\/span><\/p>\n\n\n\n
    Did You Know: Fabless chip design is the key enabler of semiconductor value chain<\/u><\/strong><\/span><\/p>\n

    In the electronics value chain, fabless semiconductor companies hold the highest strategic value because they design the chips that drive product intelligence, efficiency, and security. While fabs manufacture silicon and EMS firms assemble devices, more than half of a semiconductor\u2019s value comes from design and IP, not physical production. Fabless semiconductor design models generate high value addition with relatively modest capital expenditure, as design and IP contribute disproportionately to product economic value.<\/strong><\/span><\/p>\n

    Without strong fabless capability, a nation remains dependent on imported core technologies even if electronics are manufactured locally. Building a robust fabless ecosystem therefore enables India to own the most critical layer of the value chain, retain intellectual property, reduce imports, attract manufacturing, and establish long-term technological leadership.<\/strong><\/span><\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

    \n

    DLI Scheme<\/strong><\/span><\/p>\n

    The Design Linked Incentive (DLI) Scheme is a key instrument in advancing India\u2019s ambition to develop a strong fabless capability. The scheme is implemented by the Ministry of Electronics and Information Technology (MeitY) under the Semicon India Programme to catalyze a strong, self-reliant chip design ecosystem by providing financial incentives and access to advanced design infrastructure for domestic startups and MSMEs.<\/strong><\/span><\/p>\n\n\n\n\n
    ELIGIBILITY UNDER THE DLI SCHEME<\/strong><\/span><\/td>\n<\/tr>\n
    Start-ups and MSMEs\u00a0are eligible for financial incentives and design infrastructure support for semiconductor product design & deployment and\u00a0other domestic companies\u00a0are eligible for financial incentives for deploying semiconductor designs.<\/strong><\/span><\/p>\n
      \n
    • MSMEs:\u00a0Defined according to the\u00a0Ministry of Micro, Small and Medium Enterprises notification, 1 June 2020.<\/strong><\/span><\/li>\n
    • Startups:\u00a0Defined as per the Department for Promotion of Industry and Internal Trade (DPIIT) notification, 19 February 2019.<\/strong><\/span><\/li>\n
    • Domestic companies:\u00a0Defined as those which are owned by\u00a0resident Indian citizens, as per the Foreign Direct Investment (FDI) Policy Circular, 2017 or extant norms.<\/strong><\/span><\/li>\n<\/ul>\n<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

      The DLI Scheme supports semiconductor design across the full lifecycle\u2014from design and development to deployment\u2014covering Integrated Circuits (ICs), chipsets, Systems-on-Chip (SoCs), systems and IP cores. By promoting indigenous semiconductor content and intellectual property in electronic products, the scheme aims to reduce import dependence, strengthen supply chain resilience, and enhance domestic value addition.<\/strong><\/span><\/p>\n

      \n

      Financial Incentives and Design Infrastructure Support under DLI<\/strong><\/span><\/p>\n\n\n\n\n\n\n\n\n
      FINANCIAL INCENTIVES<\/strong><\/span><\/td>\n<\/tr>\n
      Product Design Linked Incentive<\/strong><\/span><\/td>\nDeployment Linked Incentive<\/strong><\/span><\/td>\n<\/tr>\n
      Reimbursement of up to 50% of eligible expenditure.<\/strong><\/span><\/p>\n
        \n
      • The reimbursement is capped at \u20b915 crore per application.<\/strong><\/span><\/li>\n
      • The support is available to entities involved in semiconductor design for: Integrated Circuits (ICs) Chipsets Systems on Chips (SoCs) Systems & IP Cores Semiconductor-linked designs.<\/strong><\/span><\/li>\n<\/ul>\n<\/td>\n
      		\n
        \n
      • Incentives of 6% to 4% of net sales turnover are provided for five years.<\/strong><\/span><\/li>\n
      • The incentive is capped at \u20b930 crore per application.<\/strong><\/span><\/li>\n
      • The minimum cumulative net sales required over Years 1\u20135 is 1 crore for startups\/ \u20b9 MSMEs and 5 crore for other domestic companies.<\/strong><\/span><\/li>\n
      • The design must be successfully deployed in electronic products.<\/strong><\/span><\/li>\n<\/ul>\n<\/td>\n<\/tr>\n
       <\/td>\n<\/tr>\n
      DESIGN INFRASTRUCTURE SUPPORT<\/strong><\/span><\/td>\n<\/tr>\n
      C-DAC has established the ChipIN Centre\u00a0under the DLI Scheme to facilitate the design infrastructure support to approved companies::<\/strong><\/span><\/p>\n
        \n
      • National EDA (Electronic Design Automation) Tool Grid:\u00a0Remote access to the centralized facility of advance EDA tools for chip design activities will be provided to start-ups and MSMEs.<\/strong><\/span><\/li>\n
      • IP Core repository:\u00a0Flexible access to the repository of IP Cores for SoC design activities.<\/strong><\/span><\/li>\n
      • MPW Prototyping support:\u00a0Fiscal support for fabricating the design in MPW manner at semiconductor foundries.<\/strong><\/span><\/li>\n
      • Post-silicon validation support:\u00a0Fiscal support for testing and validation of the fabricated ASIC and silicon bring-up activities.<\/strong><\/span><\/li>\n<\/ul>\n<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

        Programme Highlights & Key\u00a0Achievements\u00a0of DLI<\/strong><\/span><\/p>\n

        Since its launch in December 2021, the Design Linked Incentive (DLI) Scheme has been instrumental in shaping a stronger and more self-reliant semiconductor design ecosystem in India. By extending financial incentives, access to advanced design tools, and prototyping support to companies, startups, and academic institutions, the scheme enables innovators to progress seamlessly from ideas to actual silicon chips. This ecosystem-driven approach has been anchored by the creation of shared national infrastructure for chip design.<\/strong><\/span><\/p>\n

        A key pillar of this infrastructure is the ChipIN Centre, which has democratized access to advanced EDA tools for chip design for about 1 lakh engineers and students across 400 organizations nationwide\u2014making it the world\u2019s largest user base of a centralized chip design facility. This includes support to around 305 academic institutions under the Chips to Start-up (C2S) Programme and 95 startups under the DLI Scheme, significantly reducing entry barriers for early-stage innovators.<\/strong><\/span><\/p>\n

        Complementing this effort, India\u2019s shared EDA Grid\u2014a national platform offering high-end chip design software\u2014has recorded 54,03,005 hours of cumulative usage by 95 supported start-ups as of 2nd January 2026, reflecting strong adoption by startups, MSMEs, and researchers across all States.<\/strong><\/span><\/p>\n

        These enabling measures have translated into tangible outcomes for the domestic startup ecosystem. Supported companies under the DLI Scheme have moved from innovation to execution, with ten patents filed,\u00a016 chip-design tape-outs completed, and\u00a0six semiconductor chips successfully fabricated\u2014marking critical milestones from concept to silicon. In parallel,\u00a0over 1,000 specialised engineers have been trained or engaged through DLI-supported projects, strengthening India\u2019s design talent base. Beneficiaries have also developed more than\u00a0140 reusable semiconductor IP cores, which serve as critical enablers for advanced chip development.<\/strong><\/span><\/p>\n

        Building on these successes, the DLI Scheme is now driving the transition from design validation to productization, enabling start-ups and MSMEs to move toward volume manufacturing, system integration, and market deployment. This evolving ecosystem not only strengthens India\u2019s domestic semiconductor capabilities but also positions the country as a credible player in global chip design and innovation.<\/strong><\/span><\/p>\n

        Key Institutional Frameworks for Semiconductor Design<\/strong><\/span><\/p>\n

        India\u2019s semiconductor ecosystem is being strengthened through a coordinated institutional framework that combines policy leadership, investment support, capacity building, and indigenous technology development. Key programmes and agencies provide end-to-end backing\u2014from incentivizing chip design and manufacturing to developing skilled talent and fostering open-source microprocessor architectures\u2014ensuring India\u2019s progression toward a self-reliant and globally competitive semiconductor design ecosystem.<\/strong><\/span><\/p>\n

          \n
        1. Ministry of Electronics and Information Technology (MeitY):\u00a0MeitY leads national semiconductor initiatives, provides policy direction, and anchors schemes. It also coordinates institutional and industry partnerships to strengthen India\u2019s chip design and manufacturing ecosystem. MeitY has announced the Design Linked Incentive (DLI) Scheme; aims to offset the existing disabilities in India\u2019s domestic semiconductor design industry. It seeks to help Indian companies move up the semiconductor value chain.<\/strong><\/span><\/li>\n
        2. Semicon India Programme (SIM):\u00a0With an outlay of \u20b976,000 crore, the programme supports investments in semiconductor and display manufacturing as well as the design ecosystem. The DLI Scheme operates under this programme, ensuring end-to-end backing for design, fabrication and productisation. C-DAC, a premier R&D organization of the MeitY, is responsible for implementation of the DLI Scheme as Nodal Agency.<\/strong><\/span><\/li>\n
        3. Chips to Startup (C2S) Programme: C2S is an umbrella capacity building programme initiated at academic organizations spread across the country to generate 85 thousand number of industry-ready manpower at B.Tech, M.Tech, and PhD levels specialized in semiconductor chip design.<\/strong><\/span><\/li>\n
        4. Microprocessor Development Programme: The Microprocessor Development Programme,<\/strong><\/span><\/li>\n<\/ol>\n

          initiated at C-DAC, IIT Madras and IIT Bombay has resulted into design, development and fabrication of open-source architecture-based family of microprocessors viz. VEGA12, SHAKTI13 and AJIT microprocessors as a step towards self-reliance.<\/strong><\/span><\/p>\n

          Together, these institutional initiatives create a robust foundation for India\u2019s semiconductor ambitions, enabling startups, MSMEs, and academic institutions to innovate and scale. By bridging the gap from research to productization, they are driving self-reliance, enhancing global competitiveness, and positioning India as a strategic player in the global semiconductor landscape.<\/strong><\/span><\/p>\n

          \n

          Success Stories of India\u2019s Design Linked Incentive (DLI) Scheme<\/strong><\/span><\/p>\n

          Under the DLI scheme,\u00a024 chip-design projects have been sanctioned across areas such as video surveillance, drone detection, energy meters, microprocessors, satellite communications, and broadband and IoT SoCs.\u00a0Additionally,\u00a095 companies have received access to industry-grade EDA tools, significantly reducing design and infrastructure costs for Indian chip design startups. Among the beneficiaries, following companies stands out as leading examples of how the DLI Scheme is nurturing world-class semiconductor innovation:<\/strong><\/span><\/p>\n

            \n
          • Vervesemi Microelectronics, with a\u00a0strong portfolio of 110+ semiconductor IPs, 25 integrated circuit (IC) product variants, 10 granted patents, and 5 trade secrets\u00a0is developing motor-control chips for a wide range of applications, including consumer appliances such as fans, coolers, mixer grinders, air conditioners, washing machines, and drones, as well as automotive applications like e-scooters and e-rickshaws. These chips support a unique class of BLDC motors. Vervesemi has\u00a0completed pilot-lot sampling for two chips, with a third chip expected from the foundry later this year\u00a0and has several global customers already engaged in product development using the existing chips.<\/strong><\/span><\/li>\n
          • InCore Semiconductors\u00a0is focused on the design and development of indigenous RISC-V microprocessor IPs and SoC design automation tools, with the ultimate goal of building India\u2019s most powerful embedded processor, Dolomite, targeted at entry-level smartphones and edge-AI applications. InCore\u2019s portfolio of processor IP cores is silicon-proven across multiple customer chips, fabricated at technology nodes ranging from 180 nm to 16 nm, and aims to reduce India\u2019s dependence on imported CPU IP while enabling strategic and commercial applications.<\/strong><\/span><\/li>\n
          • Netrasemi is\u00a0focused on\u00a0designing AI-capable SoCs for CCTV secure surveillance, smart sensors, robotics and drones, and mobility applications. The company has successfully taped out India\u2019s first indigenously designed AI SoC in an advanced 12 nm process node, integrating in-house AI\/ML accelerators, vision processing, and video engines.\u00a0Netrasemi is also backed by the largest private venture capital funding to date for an Indian semiconductor company and has a series of design tape-outs\u00a0lined up next year, ranging from low-end to high-complexity surveillance SoCs.<\/strong><\/span><\/li>\n
          • Aheesa Digital Innovations\u00a0is developing Vihaan, an indigenous fiber-broadband solution used to connect homes and businesses to high-speed fiber networks.\u00a0Vihaan is built around an indigenous VEGA processor\u2013based Gigabit Passive Optical Network (GPON) Optical Network Terminal (ONT) and Network SoC, which integrates fiber termination, data processing, and network management functions into a single chip. This enables reliable, secure, and cost-effective broadband connectivity. They are on track to introduce reference platforms for customer exploration in 2026.<\/strong><\/span><\/li>\n
          • AAGYAVISION is designing advanced radar-on-chip\u00a0that operate reliably in all weather conditions, driving advancements in safety, security, smart infrastructure, edge computing, and emerging 6G sensor networks as well as critical application like drone detection.<\/strong><\/span><\/li>\n<\/ul>\n

            The success stories illustrate how the DLI Scheme is converting indigenous chip design capabilities into silicon-proven, market-ready products. By supporting advanced design, prototyping, and commercialization, the scheme is strengthening India\u2019s technological self-reliance and its position in the global semiconductor design ecosystem.<\/strong><\/span><\/p>\n

            \n

            Conclusion<\/strong><\/span><\/p>\n

            The Design Linked Incentive (DLI) Scheme is critical to anchoring India in the most strategic and value-intensive segment of the global semiconductor value chain\u2014chip design. By reducing dependence on imported semiconductor IPs and chips, strengthening resilience against geopolitical and supply-chain disruptions, and ensuring assured access to critical technologies for defence, telecom, AI and mobility, DLI lays the foundation for strategic autonomy and long-term economic growth. The scheme also enables high-value growth by translating deep-tech innovation into globally competitive products, fostering startups and MSMEs, and building a highly skilled engineering workforce.<\/strong><\/span><\/p>\n

            These outcomes are already evident, with DLI-supported firms achieving multiple chip tape-outs, silicon-proven designs, patents, reusable IPs, trained talent and operational design infrastructure, demonstrating tangible on-ground impact. As the ecosystem enters the productization phase, silicon-validated designs are moving toward volume manufacturing, system integration and market deployment, positioning Indian companies as credible global suppliers while strengthening domestic supply chains and reinforcing India\u2019s self-reliant semiconductor ecosystem.<\/strong><\/span><\/p>\n","protected":false},"excerpt":{"rendered":"

            Design Linked Incentive Scheme Catalyzing India\u2019s Semiconductor Design Ecosystem Posted On: 04 JAN 2026 12:18PM by PIB Delhi Key Takeaways Semiconductor chip\u00a0design is the main value driver, contributing up to\u00a050% of value addition,\u00a020\u201350% of Bill of Materials\u00a0cost (BOM), and\u00a030\u201335% of global semiconductor sales\u00a0via the fabless segment. MeitY\u2019s Design Linked Incentive (DLI) Scheme\u00a0under the\u00a0Semicon India Programme\u00a0aims …<\/p>\n","protected":false},"author":2,"featured_media":16325,"comment_status":"open","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[1],"tags":[],"class_list":["post-16324","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-education-news"],"_links":{"self":[{"href":"https:\/\/theeducationoverview.in\/index.php?rest_route=\/wp\/v2\/posts\/16324","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/theeducationoverview.in\/index.php?rest_route=\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/theeducationoverview.in\/index.php?rest_route=\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/theeducationoverview.in\/index.php?rest_route=\/wp\/v2\/users\/2"}],"replies":[{"embeddable":true,"href":"https:\/\/theeducationoverview.in\/index.php?rest_route=%2Fwp%2Fv2%2Fcomments&post=16324"}],"version-history":[{"count":1,"href":"https:\/\/theeducationoverview.in\/index.php?rest_route=\/wp\/v2\/posts\/16324\/revisions"}],"predecessor-version":[{"id":16326,"href":"https:\/\/theeducationoverview.in\/index.php?rest_route=\/wp\/v2\/posts\/16324\/revisions\/16326"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/theeducationoverview.in\/index.php?rest_route=\/wp\/v2\/media\/16325"}],"wp:attachment":[{"href":"https:\/\/theeducationoverview.in\/index.php?rest_route=%2Fwp%2Fv2%2Fmedia&parent=16324"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/theeducationoverview.in\/index.php?rest_route=%2Fwp%2Fv2%2Fcategories&post=16324"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/theeducationoverview.in\/index.php?rest_route=%2Fwp%2Fv2%2Ftags&post=16324"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}